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Description
As a Processor Power Management Verification Engineer, you will have the responsibilities as follows: - Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic - Develop and execute test plans and schedules for the power management and clock control logic - Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments - Root cause failures and propose potential solution to the design team - Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design - Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered - Develop checkers or Verilog/System Verilog-base transactor to verify the design - Write assertions and apply formal verification to the design
Minimum Qualifications
- Minimum BS - Experience with digital logic, micro-processor architecture, or power management architecture - Experience with digital design verification including knowledge of Verilog/System-Verilog based testbenches, transactors checkers - Programming skills include scripting languages such as Perl or Python
Preferred Qualifications
- Master’s degree preferred - Experience in processor or power management architecture and verification - In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches - Experience in system Verilog assertions or silicon bringup or UPF and low power simulation - Experience with advanced verification techniques such as formal verification is a plus - Advanced programming skills such as object orientated programming or CPU assembly language is a plus - Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort - Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design
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