SRAM Physical Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

THE PERSON:

KEY RESPONSIBILITIES:

• Contribute to the physical design and implementation of high-speed SRAM and memory structures for advanced CPU products.
• Work closely with architecture, RTL, circuit design, and physical design teams to optimize power, performance, area, and schedule.
• Perform floorplanning, placement, clock tree synthesis, routing, timing closure, and design optimization activities.
• Analyze and resolve implementation, timing, power, and signoff challenges.
• Develop creative solutions to complex design and tool-related problems.
• Contribute to methodology and flow improvements that increase design quality and efficiency.
• Create and deliver technical presentations, design reviews, and documentation for engineering teams and management.

• Support physical verification, extraction, reliability analysis, and design signoff activities.

   

PREFERRED EXPERIENCE:

• Experience with high-speed SRAM design, memory design, or memory-centric physical implementation.
• Strong understanding of CPU, cache, or other performance-critical digital designs.
• Strong understanding of computer architecture, hardware design concepts, and performance, power, and area tradeoffs.
• Knowledge of chip-level floorplanning, bus and pin planning, clock tree synthesis, placement, optimization, routing, and timing closure.
• Experience with parasitic extraction, static timing analysis, physical verification, and design signoff methodologies.
• Familiarity with power integrity analysis, including IR-drop and electromigration.
• Ability to comprehend complex Verilog RTL and make modifications to support timing, power, or implementation objectives.
• Knowledge of digital circuits, including high-speed flops, synchronizers, level shifters, and SRAM.
• Experience using industry-standard EDA tools for physical design and implementation.
• Familiarity with scripting or programming languages such as Tcl, Perl, C, Python, or similar.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.