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FE Engineer

Apple
Posted 16 hours ago, valid for a month
Location

Austin, TX, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • Apple is seeking a SoC Front End Design Integration Engineer to design, integrate, and verify a system fabric bus into a subsystem.
  • Candidates should possess digital logic design knowledge, experience with Verilog/System Verilog, and familiarity with Synopsys/Cadence tools.
  • The role requires strong problem-solving and analytical skills, as well as effective communication and teamwork abilities.
  • Preferred qualifications include experience in writing specifications, verifying logic design hardware, and exposure to front-end tools and methodologies.
  • The position offers a competitive salary and requires a minimum of 5 years of relevant experience.
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. As a SoC Front End Design Integration Engineer you will be designing, integrating, and verifying a system fabric bus into a subsystem. In this role, you will need to define and build this platform with flexibility and reusability in mind.

Description


* Building a test bench, creating test vectors, and running the verification environment to verify that the subsystem you designed works properly * Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirements * Designing, integrating, and verifying a system fabric bus into a subsystem

Minimum Qualifications


Digital Logic Design knowledge Verilog/System Verilog RTL language design entry Synopsys/Cadence synthesis Synopsys PrimeTime Static Timing Analysis (STA) Synopsys (VCS)/Cadence(Incisive) simulation Strong problem solving and analytical skills Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design

Preferred Qualifications


* Experience/exposure writing specifications and documentation * Experience/exposure with verifying logic design hardware * Experience/exposure to front-end tools and methodologies


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